1. Field of the Invention
The present invention relates generally to nonvolatile semiconductor read only memory (ROM) systems and, more particularly, relates to an improved electrically erasable programmable read only memory (E.sup.2 PROM).
2. Description of the Relevant Art
A great amount of research is being directed to improving E.sup.2 PROM memory systems. It is anticipated that these systems will eventually replace disk drives thereby substantially reducing the cost and read access time of storage in digital systems.
An E.sup.2 PROM cell is essentially an MOS transistor including source and drain diffusions coupled by a channel, a word line positioned over the channel, and a programmable floating gate positioned under the word line and above the channel. The cell stores a first binary state when the floating gate is charged with excess electrons and stores a second binary state when the floating gate is not charged with excess electrons.
During a read operation, the drain diffusion is charged to VD(R) and the word line is charged to VWL(R). If the floating gate is not charged, then the channel is inverted, current flows between the source and drain, and the voltage level of the drain diffusion decreases. This decrease is sensed to indicate that the second binary state is stored in the cell. If the floating gate is charged, then the threshold voltage of the MOS transistor is increased, the channel is not inverted, no current flows between the source and drain, and the voltage level of the drain diffusion does not decrease. This voltage level is sensed and indicates that the first binary state is stored in the cell.
Two methods utilized to charge the floating gate will now be described. The first method is to increase the potential difference between the source and drain diffusion to a level that induces avalanche breakdown at the drain junction. High energy electrons (hot electrons) will penetrate the oxide layer separating the floating gate from the channel and program the floating gate.
The second method is to cause electrons to tunnel from a grounded programming poly diffusion to the floating gate through a special tunnelling oxide layer. This tunnelling method requires three poly layers. The first layer is grounded and provides electrons during the charging operation, the second layer forms the floating gates, and the third layer forms the word lines. A select transistor must be included in each cell to allow discharging the the floating gate of a single cell in a row.
The discharging of the floating gates will now be described. In the hot electron embodiment, the word line is charged to a relatively high erase voltage level VWL(E) and the floating gate is capacitively coupled to a grounded drain electrode through the isolation oxide. Electrons then tunnel from the floating gate to the word line through a tunnelling oxide layer. Similarly, in the tunnelling embodiment, the first poly layer is grounded and the second poly layer is coupled to ground via high capacitive ratio between the layers. The word line is charged to VWL(E) and electrons tunnel from the floating gate to the word line.
Both types of systems have advantages and drawbacks. Turning first to the hot electron type of system, the structure only requires two poly layers and is thus easier to fabricate. However, hot electrons transferred via the oxide damage the oxide thereby reducing the number of programming cycles. Additionally, the production of hot electrons requires an off-chip power source capable of generating significant current. Further, the weak coupling of the floating gate to ground requires that the magnitude of the erase voltage be high. When arranged in an array matrix, selective cells cannot be eased without the erasure of the entire array.
Turning next to the tunnelling system, the program and erase operations are less stressful to the oxide and more cycles are possible. Additionally, less current is drawn than in the hot electron system. However, during the erase operation extraneous electrons tunnel from the first poly to the word line and thus cause excess stress to the oxide and higher than necessary current flow. Further, the three poly layer structure is complex and requires four control signal contacts, i.e., source, drain, word line, and select.
In view of the above, it is apparent that an improved E.sup.2 PROM system facilitating the use of an on-chip power supply, utilizes only two poly layers, and provides for a high number of program cycles is greatly required.